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femtoclocks? crystal-to- 3.3v lvpecl clock generator ics843001 idt ? / ics ? 3.3v lvpecl clock generator 1 ics843001ag rev b march 2, 2009 g eneral d escription the ics843001 is a fibre channel clock generator and a member of the hiperclocks tm family of high performance devices from idt. the ics843001 uses either a 26.5625mhz or a 23.4375 crystal to synthesize 106.25mhz, 187.5mhz or 212.5mhz, using the freq_sel pin. the ics843001 has excellent <1ps phase jitter performance, over the 637khz ? 10mhz integration range. the ics843001 is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. f eatures ? one differential 3.3v lvpecl output ? crystal oscillator interface designed for 23.4375mhz or 26.5625mhz, 18pf parallel resonant crystal ? selectable 106.25mhz, 187.5mhz or 212.5mhz output frequency ? vco range: 560mhz - 680mhz ? rms phase jitter @ 106.255mhz, using a 26.5625mhz crystal (637khz - 10mhz): 0.74ps (typical) ? rms phase noise at 106.25mhz phase noise: offset noise p o w er 100hz ............... -95.2 dbc/hz 1khz ............. -118.7 dbc/hz 10khz ............. -129.1 dbc/hz 100khz ............. -129.6 dbc/hz ? 3.3v operating supply ? -30c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s s t u p n i s e i c n e u q e r f t u p t u o y c n e u q e r f l a t s y r cl e s _ q e r f z h m 5 2 6 5 . 6 20 ) t l u a f e d ( z h m 5 2 . 6 0 1 z h m 5 2 6 5 . 6 21z h m 5 . 2 1 2 z h m 5 7 3 4 . 3 21z h m 5 . 7 8 1 f unction t able ics843001 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view v cca v ee xtal_out xtal_in 1 2 3 4 v cc q0 nq0 freq_sel 8 7 6 5 osc phase detector vco 637.5mhz w/ 26.5625mhz ref. m = 24 (fixed) 1 0 6 3 b lock d iagram p in a ssignment xtal_in xtal_out nq0 q0 freq_sel (pulldown)
idt ? / ics ? 3.3v lvpecl clock generator 2 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator t able 2. p in c haracteristics t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 1v a c c r e w o p. n i p y l p p u s g o l a n a 2v e e r e w o p. n i p y l p p u s e v i t a g e n , 3 4 , t u o _ l a t x n i _ l a t x t u p n i , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x 5l e s _ q e r ft u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f 7 , 60 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d 8v c c r e w o p. n i p y l p p u s e r o c : e t o n n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ?
idt ? / ics ? 3.3v lvpecl clock generator 3 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator t able 3a. p ower s upply dc c haracteristics , v cc = 3.3v5%, t a = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v i a c c t n e r r u c y l p p u s g o l a n ai n i d e d u l c n i e e 2 1a m i e e t n e r r u c y l p p u s r e w o p 3 9a m t able 3c. lvpecl dc c haracteristics , v cc = 3.3v5%, t a = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - t able 4. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 7 3 4 . 3 25 2 6 5 . 6 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 ? e c n a t i c a p a c t n u h s 7f p a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o contin uous current 50ma surge current 100ma package thermal impedance, ja 101.7c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 3b. lvcmos/lvttl dc c haracteristics , v cc = 3.3v5%, t a = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n il e s _ q e r fv c c v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n il e s _ q e r fv c c v , v 5 6 4 . 3 = n i v 0 =5 -a
idt ? / ics ? 3.3v lvpecl clock generator 4 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator t able 5. ac c haracteristics , v cc = 3.3v5%, t a = -30c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 1 = l e s _ q e r f7 6 . 6 8 16 6 . 6 2 2z h m 0 = l e s _ q e r f3 3 . 3 93 3 . 3 1 1z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 1 e t o n ) z h m 0 1 o t z h k 7 3 6 ( , z h m 5 . 2 1 27 6 . 0s p ) z h m 0 2 o t z h m 5 7 8 . 1 ( , z h m 5 . 7 8 12 5 . 0s p ) z h m 0 1 o t z h k 7 3 6 ( , z h m 5 2 . 6 0 14 7 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 6s p c d oe l c y c y t u d t u p t u o 0 = l e s f8 42 5% 1 = l e s f5 45 5% . t o l p e s i o n e s a h p o t r e f e r e s a e l p : 1 e t o n
idt ? / ics ? 3.3v lvpecl clock generator 5 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator o ffset f requency (h z ) dbc hz n oise p ower 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m t ypical p hase n oise at 212.5mh z 212.5mhz rms phase noise jitter 637k to 10mhz = 0.67ps (typical) phase noise result by adding fibre channel filter to raw data raw phase noise data fibre channel filter ? ? ? t ypical p hase n oise at 106.25mh z 106.25mhz rms phase jitter (random) 637khz to 10mhz = 0.74ps (typical) o ffset f requency (h z ) dbc hz n oise p ower 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m phase noise result by adding fibre channel filter to raw data raw phase noise data fibre channel filter ? ? ?
idt ? / ics ? 3.3v lvpecl clock generator 6 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator o ffset f requency (h z ) dbc hz n oise p ower 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m t ypical p hase n oise at 187.5mh z 187.5mhz rms phase noise jitter 1.875mhz to 20mhz = 0.52ps (typical) phase noise result by adding 10 gigabit ethernet filter to raw data raw phase noise data 10 gigabit ethernet filter ? ? ?
idt ? / ics ? 3.3v lvpecl clock generator 7 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator p arameter m easurement i nformation o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl v ee 2v -1.3v 0.165v clock outputs 20% 80% 80% 20% t r t f v sw i n g pulse width t period t pw t period odc = q0 nq0 v cc rms p hase j itter phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power
idt ? / ics ? 3.3v lvpecl clock generator 8 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator a pplication i nformation f igure 2. c rystal i npu t i nterface c rystal i nput i nterface the ics843001 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 26.5625mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843001 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc and v cca should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 ? resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 ? v cca 10 f .01 f 3.3v .01 f v cc c1 33p x1 18pf parallel crystal c2 27p xtal_out xtal_in
idt ? / ics ? 3.3v lvpecl clock generator 9 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator f igure 3a. ics843001 s chematic e xample l ayout g uideline figure 3a shows a schematic example of the ics843001. an example of lvepcl termination is shown in this schematic. additional lvpecl termination approaches are shown in the lvpecl termination application note. in this example, an 18pf parallel resonant crystal is used. the c1 = 27pf and c2 = 33pf are recommended for frequency accuracy. the c1 and c2 values may be slightly adjusted for optimizing frequency accuracy. f igure 3b. ics843001 pc b oard l ayout e xample vcca c1 27pf nq c4 0.01u q r5 133 r1 1k zo = 50 ohm vcc r6 82.5 18pf c5 0.1u c3 10uf + - u1 ics843001 1 2 3 4 8 7 6 5 vcca vee xtal _o u t xtal _i n vcc q0 nq0 freq_sel vcc r3 133 r4 82.5 vcc zo = 50 ohm x1 26.5625mhz r2 10 vcc c2 33pf pc b oard l ayout e xample figure 3b shows an example of ics843001 p.c. board layout. the crystal x1 footprint shown in this example allows installation of either surface mount hc49s or through-hole hc49 package. the footprints of other components in this example are listed in the table 6. there should be at least one decoupling capacitor per power pin. the decoupling capacitors should be located as close as possible to the power pins. the layout assumes that the board has clean analog power ground plane. t able 6. f ootprint t able e c n e r e f e re z i s 2 c , 1 c2 0 4 0 3 c5 0 8 0 5 c , 4 c3 0 6 0 2 r3 0 6 0 t n e n o p m o c s t s i l , 6 e l b a t : e t o n . e l p m a x e t u o y a l s i h t n i n w o h s s e z i s
idt ? / ics ? 3.3v lvpecl clock generator 10 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843001. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843001 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 93ma = 322.2mw ? power (outputs) max = 30mw/loaded output pair total power _max (3.465v, with all outputs switching) = 322.2mw + 30mw = 352.2mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.352w * 90.5c/w = 116.9c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 7. t hermal r esistance ja for 8- pin tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
idt ? / ics ? 3.3v lvpecl clock generator 11 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 4. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc - 2v. for logic high, v out = v oh_max = v cc_max ? 0.9v (v cco_max - v oh_max ) = 0.9v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 4. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
idt ? / ics ? 3.3v lvpecl clock generator 12 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator r eliability i nformation t ransistor c ount the transistor count for ics843001 is: 1702 t able 8. ja vs . a ir f low t able for 8 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
idt ? / ics ? 3.3v lvpecl clock generator 13 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator p ackage o utline - g s uffix 8 l ead tssop t able 9. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 20 1 . 3 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? 3.3v lvpecl clock generator 14 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t g a 1 0 0 3 4 8 s c ia 1 0 0 3p o s s t d a e l 8e b u tc 5 8 o t c 0 3 - t g a 1 0 0 3 4 8 s c ia 1 0 0 3p o s s t d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 3 - f l g a 1 0 0 3 4 8 s c il a 1 0 0p o s s t " e e r f - d a e l " d a e l 8e b u tc 5 8 o t c 0 3 - t f l g a 1 0 0 3 4 8 s c il a 1 0 0p o s s t " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 3 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
idt ? / ics ? 3.3v lvpecl clock generator 15 ics843001ag rev b march 2, 2009 ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a1 . m a r g a i d k c o l b d e t c e r r o c 4 0 / 1 / 6 ba 3 t3 . c e p s a c c i d e d d a - e l b a t s c i t s i r e t c a r a h c c d y l p p u s r e w o p 4 0 / 3 2 / 8 b0 1 t4 1 . e b u t r e p 0 0 1 o t 4 5 1 m o r f t n u o c d e t c e r r o c - e l b a t n o i t a m r o f n i g n i r e d r o 4 0 / 3 1 / 0 1 b 0 1 t 1 4 1 . n o i t c e s s e r u t a e f n i t e l l u b e e r f - d a e l d e d d a . t r a p " e e r f - d a e l " d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 4 0 / 4 1 / 2 1 b 0 1 t4 1 m o r f g n i k r a m & r e b m u n r e d r o / t r a p d e t c e r r o c - e l b a t n o i t a m r o f n i g n i r e d r o . " g b . . " o t " g a . . " 6 0 / 4 0 / 2 1 b 0 1 t4 1 o t k c a b g n i k r a m & r e b m u n r e d r o / t r a p d e g n a h c - e l b a t n o i t a m r o f n i g n i r e d r o . " g b . . " m o r f " g a " 6 0 / 6 0 / 2 1
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics843001 femtoclocks? crystal-to-3.3v lvpecl clock generator

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